We are seeking a skilled Analog Layout Engineer to contribute to the design and development of full-custom analog IP blocks.
Key Responsibilities:
* Design and develop custom analog layouts such as PLL, Bandgap References (BG), LVDS, IVREF, and more across various projects.
* Execute physical verification checks including DRC, LVS, EM-IR analysis, and others applicable to your designs.
* Carry out floorplanning and top-level routing, taking into account power domains and the intricacies of mixed-signal designs.
* Conduct CHIP-level validations, including post-dummy fill and other tape-out signoff checks.
* Ensure timely delivery of layout blocks and all necessary project deliverables to meet critical deadlines.
* Compile design reports and complete formal checklists at project closure.
Location: Leuven, Belgium
Requirements:
* Proven hands-on experience with analog layout design and top-level integration.
* Proficiency in EDA tools used for layout and verification.
* Solid understanding of Layout Dependent Effects (LDEs), especially in deep submicron technology nodes.
* Detail-oriented mindset with the ability to work independently and collaboratively.
* Willingness to travel regularly (approximately one week per month) to visit subcontractors.
We Offer:
* A dynamic opportunity to be part of cutting-edge analog design projects that shape future technology.
* Assignment Type: Full-time.
* Work Schedule: 40 hours per week.
* A flexible hybrid work environment.
* Work Environment: A supportive and innovative team culture that promotes work-life balance and continuous learning.