For our client pushing the boundaries of chip design and testing we're recruiting a Senior DFT Engineer to work on advanced 3D integration technologies, ensuring testability and reliability in next-generation semiconductor systems
Your Role
* Design and optimize DFT (Design for Test) strategies for digital, memory, and analog IPs.
* Develop and validate test methods for 3DIC architectures and interconnects.
* Analyze faults, defect mechanisms, and failure behaviors across system layers.
* Contribute to system-level DFX (Design for Excellence) strategies and test implementation.
What We’re Looking For
* 5–10 years’ experience in semiconductor testing, DFT, or reliability engineering.
* Strong knowledge of MBIST, SCAN, ATPG, fault modeling, and failure analysis.
* Background in digital, memory, or analog ICs, ideally including 3DIC or IO interconnects.
* Master's degree or higher in Electronics, Microelectronics, Physics, or related fields.
Why Join
* Shape the future of high-performance, stacked chip systems.
* Work in a cutting-edge R&D environment on breakthrough technologies.
* Join a collaborative, global team focused on innovation and excellence.
Contact
Philippe BILDÉ
Antal International Paris London
Philippe.Bilde@antal.com
www.antal.com/recruitment/france-paris-bsc