Join VeroTech as a Sr. Physical Design Engineer and become part of our community where innovation and people come first. You’ll take on exciting technical challenges and develop your expertise while creating solutions that drive progress across several industries.
About The Role
As a Sr. Physical Design Engineer, you lead the full RTL-to-GDSII physical implementation flow. Define and execute implementation strategies optimized for SoC FinFET technologies, addressing challenges such as secondary power grids, track patterns, and advanced DRC constraints. You will mentor a team of backend designers.
Key Responsibilities
* Lead the full RTL-to-GDSII physical implementation flow from synthesis to floorplanning, place & route, CTS, timing closure, and sign-off.
* Perform MMMC timing closure and power optimization to meet PPA targets.
* Conduct power integrity analysis, ensure robust IR drop & EM margins.
* Collaborate with RTL and DFT teams.
* Interface with external stakeholders, like foundries and EDA vendors.
* Contribute to EDA flow improvements and automation.
What we’re looking for
* A Master’s in Electrical Engineering or related field and over 10 years in full-custom layout for memory and/or analog/mixed-signal IPs are required.
* Deep understanding of physical constraints: matching, EM, IR drop, antenna rules.
* Proficient in layout tools & scripting (layout: Virtuoso, Calibre, scripting: TCL/Perl, LabView or Python).
* Experience with advanced CMOS nodes and emerging memories (MRAM, RRAM) is advantageous.
* Experience in in-memory computing layout is a plus.
* Excellent communication skills in English; French and/or Dutch is a bonus.
* Willingness to travel abroad occasionally is required.
Benefits
* Remote work options
* Competitive salary package
* Meal vouchers
* Insurance
* Company car
* Work‑life balance support
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