Physical Design Engineer
6 month rolling contract
Belgium
Onsite requirement
An advanced semiconductor development environment is seeking a Senior ASIC Back-End Design Engineer for a temporary engagement. The successful candidate will play a key role in executing and optimizing the complete RTL-to-GDSII implementation flow for complex digital IC designs.
You will collaborate within a highly technical engineering team delivering sophisticated ASIC solutions across diverse projects in an international setting.
Core Responsibilities
* Drive RTL synthesis activities with focus on performance, area efficiency, and power optimization
* Implement Design-for-Test (DFT) architectures using established industry practices
* Perform Logical Equivalence Checking (LEC) to ensure design consistency
* Develop and validate ATPG solutions to maximize fault coverage
* Analyze and enhance test coverage metrics
* Execute simulation of test patterns at both pre- and post-layout stages
* Interface closely with physical implementation teams to ensure design convergence
* Work with leading EDA environments for synthesis, verification, and test insertion
* Identify and resolve issues across the digital implementation flow
* Maintain comprehensive technical documentation
* Contribute to process improvements and engineering best practices
Required Background
* Minimum 5 years’ experience in ASIC digital implementation
* Strong knowledge of the complete RTL-to-GDSII flow
* Demonstrated expertise in synthesis, DFT, LEC, and ATPG methodologies
* Experience with industry-standard EDA toolchains
* Solid understanding of timing analysis, digital architecture, and test strategies
* Proficiency in Verilog and/or SystemVerilog
* Familiarity with scripting languages such as Tcl or Python
* Strong analytical mindset and structured problem-solving ability
* Comfortable working in cross-functional engineering environments
* Degree in Electrical Engineering, Computer Engineering, or related discipline (Master’s preferred)