Senior ASIC Design Engineer - Front EndLeuven/Hybrid6+ Month ContractEnglish & Dutch (Nice to have both languages)
Global Consultancy based in Leuven are looking for a Senior ASIC Design Engineer - Front End for a Major Engineering Client
ResponsibilitiesPerform RTL synthesis optimised for timing, area, and powerExecute DFT insertion and ATPG pattern generation using Cadence, Synopsys, or Tessent toolsConduct Logical Equivalence Checking (LEC) to validate design integrityImprove test coverage through advanced methodologiesRun pre- and post-layout test pattern simulationsCollaborate with physical design teams for seamless RTL-to-GDS integrationTroubleshoot and resolve design issues across the front-end flowDocument processes and engage with internal and external stakeholders
Job Requirements5+ years in ASIC front-end design (RTL-to-GDS flow)Proven expertise in synthesis, DFT, LEC, and ATPGHands-on experience with Cadence (Genus, Modus, Conformal) and/or Synopsys (DC, FC, TestMAX)Familiarity with Tessent (Siemens) for DFT/ATPGProficient in Verilog/SystemVerilog and scripting (Tcl, Python)Strong understanding of timing closure and test strategiesMaster's in Electrical/Computer Engineering preferredFluent in English; Dutch is a plus
All interviews will be done remotely.
This role is SUPER URGENT, don't hesitate to get in touch
You must have the right working rights as no sponsorship is on offer.
Feel free to send your cv to nelesh@wesourcetalent.com to learn more or call me on + 44 77 256 18 238