🔥Senior ASIC Design Engineer - Front End
📍Leuven/Hybrid
🚨🚨 6+ Month Contract 🚨🚨
🎁English & Dutch (Nice to have both languages)
Global Consultancy based in Leuven are looking for a Senior ASIC Design Engineer - Front End for a Major Engineering Client
Responsibilities
* Perform RTL synthesis optimised for timing, area, and power
* Execute DFT insertion and ATPG pattern generation using Cadence, Synopsys, or Tessent tools
* Conduct Logical Equivalence Checking (LEC) to validate design integrity
* Improve test coverage through advanced methodologies
* Run pre- and post-layout test pattern simulations
* Collaborate with physical design teams for seamless RTL-to-GDS integration
* Troubleshoot and resolve design issues across the front-end flow
* Document processes and engage with internal and external stakeholders
Job Requirements
* 5+ years in ASIC front-end design (RTL-to-GDS flow)
* Proven expertise in synthesis, DFT, LEC, and ATPG
* Hands-on experience with Cadence (Genus, Modus, Conformal) and/or Synopsys (DC, FC, TestMAX)
* Familiarity with Tessent (Siemens) for DFT/ATPG
* Proficient in Verilog/SystemVerilog and scripting (Tcl, Python)
* Strong understanding of timing closure and test strategies
* Master's in Electrical/Computer Engineering preferred
* Fluent in English; Dutch is a plus
All interviews will be done remotely.
🚨This role is SUPER URGENT, don't hesitate to get in touch🚨
You must have the right working rights as no sponsorship is on offer.
Feel free to send your cv to nelesh@wesourcetalent.com to learn more or call me on +44 77 256 18 238