Systems that deploy computational logic near memory can overcome typical von Neumann-based bottlenecks (e.g. memory wall) by limiting the amount of data transferred to central compute areas in a system. With modern compute-near memory (CnM) systems still in their infancy and typical programming paradigms focused on centralized computing however, new work must be undertaken to understand the architectural trade-offs and implementations of CnM systems with respect to full systems. During this research internship, you will work to augment a full system-level model of CnM hardware for evaluation of upcoming CnM-enabled workloads and technologies. Full system-level simulation of CnM hardware enables the rapid evaluation of conventional CnM targets (e.g. AI, Genomics, etc.) as well as bottleneck analysis and weighing the trade-offs of high-level architectural decisions.
Key responsibilities will include: Developing and augmenting full system-level CnM models for performance evaluation that are highly configurable and extensible to maintain relevancy with respect to emerging architectures. Collaborating with other team members on the development of CnM libraries and software to broaden research into CnM-enabled applications in a wide variety of software domains. Disseminating and evaluating different kinds of CnM architectures, weighing the performance trade-offs of different configurations and CnM-ISAs. This role is ideal for someone who is deeply interested in hardware-software codesign, computer architecture, and working in an interdisciplinary environment that values innovation, creativity, and real-world impact. Profile : You are analytical and detail-oriented, with a strong interest in system simulation and hardware-software codesign. You are adept at or have a keen interest in programming and performance evaluation tools. Background : You have or are currently pursuing a degree in computer engineering, computer science, or electrical engineering. Knowledge of object-oriented programming, scripting languages, gem5, and memory simulators is an advantage. Type of Project :Thesis; Internship; Combination of internship and thesis Master's degree :Master of Engineering Technology; Master of Science; Master of Engineering Science Master program :Computer Science; Electromechanical engineering; Electrotechnics/Electrical Engineering Duration :6-12 months Supervisor :Chris Van Hoof (EE, Nano) For more information or application, please contact the supervising scientist Joshua Klein ( joshua.klein@imec.be ). Imec allowance will be provided.
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