Job Title: Senior Digital IC Design & Verification Engineer
Position: Full time/ Permanent
Location: Belgium
The Senior Digital Design & Verification Engineer has the following responsibilities:
-Integrate legacy control and data path designs in new products
-Update and verify legacy designs to fit new product requirements
-Design and verify new ultra-high speed DSP blocks for next gen products
-Interface with the physical implementation team for further design and flow improvements
This role includes technical leadership, meaning technical hands-on expertise and excellent team skills; this candidate targets high and challenging standards on technical performance, product and process quality and project schedule.
Required Education and Experience:
-MSEE or equivalent with min 3 to 5 years industrial experience
-Solid grasp of simulation concepts such as regression testing, UVM, functional coverage, assertions, …
-Good knowledge of Verilog and SystemVerilog for design and verification
-Experience with RTL lint
-Knowledgeable about DFT and ATPG
-Knowledgeable about CDC issues and techniques for low power design
-Experience with delay annotated gatelevel simulation
-Experience with implementation of high-speed pipelined FIR DSP structures is a plus
-Formal Verification experience is a plus
&#;Formal lint
&#;Sequential Equivalence Checking
&#;Assertion Based Verification
-Experience with C/C++/SystemC models for RTL verification a must
-Python and TCL programming experience a strong plus
-Able to efficiently work in a Linux command line environment as well as in Windows MS Office for reporting and documentation
-Continuous strive for improvement in circuits and process
-Willing to relocate to Leuven (Belgium) region