Physical Design Engineer6 month rolling contractBelgiumOnsite requirement
An advanced semiconductor development environment is seeking a Senior ASIC Back-End Design Engineer for a temporary engagement. The successful candidate will play a key role in executing and optimizing the complete RTL-to-GDSII implementation flow for complex digital IC designs.You will collaborate within a highly technical engineering team delivering sophisticated ASIC solutions across diverse projects in an international setting.
Core ResponsibilitiesDrive RTL synthesis activities with focus on performance, area efficiency, and power optimizationImplement Design-for-Test (DFT) architectures using established industry practicesPerform Logical Equivalence Checking (LEC) to ensure design consistencyDevelop and validate ATPG solutions to maximize fault coverageAnalyze and enhance test coverage metricsExecute simulation of test patterns at both pre- and post-layout stagesInterface closely with physical implementation teams to ensure design convergenceWork with leading EDA environments for synthesis, verification, and test insertionIdentify and resolve issues across the digital implementation flowMaintain comprehensive technical documentationContribute to process improvements and engineering best practices
Required BackgroundMinimum 5 years' experience in ASIC digital implementationStrong knowledge of the complete RTL-to-GDSII flowDemonstrated expertise in synthesis, DFT, LEC, and ATPG methodologiesExperience with industry-standard EDA toolchainsSolid understanding of timing analysis, digital architecture, and test strategiesProficiency in Verilog and/or SystemVerilogFamiliarity with scripting languages such as Tcl or PythonStrong analytical mindset and structured problem-solving abilityComfortable working in cross-functional engineering environmentsDegree in Electrical Engineering, Computer Engineering, or related discipline (Master's preferred)