Physical ASIC Design Implementation Engineer
Learn more about the general tasks related to this opportunity below, as well as required skills.
We are looking for a Physical ASIC Design Implementation Engineer to support full back‑end (Place & Route) projects, covering the complete flow from netlist-in to GDSII-out. You will work on both top-level chips and block-level designs, across technology nodes ranging from N2 to 180nm, with a strong focus on the Cadence Innovus Place & Route flow .
This is a hands-on technical role that combines deep physical design expertise with direct customer interaction.
Execute full physical implementation flows (P&R) from netlist to GDSII for top-level and block-level designs
Work closely with the Physical Design implementation team throughout the entire chip design cycle
Proven experience in setting up physical design flows for specific library sets and foundry nodes
Experience with low-power design methodologies (UPF) and debugging xphnsxz SDC files
Floorplanning and power grid design (top-level and block-level)
Timing analysis ( Tempus )
Power analysis ( Voltus )
An exciting assignment within an advanced technology environment
A role contributing directly to technologies that will shape the society of tomorrow