We are looking for a highly skilled Digital SoC Design Engineer to join a multidisciplinary team developing next-generation ICs for IoT, Edge AI accelerators, and Health applications. In this role, you will take ownership of high-performance, ultra-low-power digital signal processing modules and contribute to innovative SoC architectures that shape the technology of tomorrow.
Your Responsibilities
* Define digital concepts and architectures for next-generation ICs.
* Develop RTL for ASIC and FPGA implementations ((System)Verilog).
* Design high-performance, ultra-low-power digital signal processing modules.
* Make architecture trade-offs to optimize:
* Power consumption
* Performance
* Cost
* Scalability, maintainability & re-usability
* Collaborate with the digital back-end team on synthesis and physical implementation.
* Define and execute verification strategies.
* Validate and characterize designs experimentally in a lab environment.
* Translate internal/external customer requirements into robust design solutions.
* Contribute to high-quality documentation and technical reports.
* Work closely within an interdisciplinary engineering team.
Required Knowledge & Experience
* MSc or PhD in Electronics Engineering.
* Minimum 5+ years of relevant industry experience.
* Strong expertise in digital circuit design using (System)Verilog.
* Solid understanding of the digital ASIC design flow:
* Logic synthesis
* Timing analysis
* Power simulation
* Logic equivalence
* DFT and/or Place & Route
* Experience with scripting languages:
* TCL
* Python
* Matlab
* Experience with version control systems (e.g., Git).
* Excellent communication skills in English (written and spoken).
Preferred Experience
* Hardware-efficient AI accelerators.
* Event-driven computing.
* Multi-core processor systems.
* In-memory computing.
* Large-scale data computing.
* Hardware modeling.
* CPU and peripheral subsystem architecture & design.
* Digital verification methodologies:
* Verification planning & tracking
* Code & functional coverage
* Constrained-random verification
* FPGA development.
* Low-power digital design techniques.
* Experience with Cadence IC design tools.
* Experience with C and SystemC.
* Structured and planning-oriented way of working.
* Experience collaborating with internal and external stakeholders.
Profile
* Proactive and self-driven.
* Creative problem-solver.
* Strong sense of ownership and responsibility.
* Comfortable working independently and in team environments.
* Broad technical curiosity and eagerness to embrace new challenges.
* Able to take initiative and contribute to team success.
It is a 6 months assignment and can get extended further based on the progress