ROLE: Lead Backend Engineer
LOCATION: Barcelona, Spain
SALARY: Negotiable
DURATION: Permanent
Description:
We are seeking experienced Physical Design Engineers with 7+ years of expertise in synthesis, place & route flows, floorplanning, and wireplanning. Proven experience with tape-outs is essential. Strong knowledge of clock tree synthesis (including custom clock trees) and proficiency with netlist power analysis tools (e.g., PrimeTime/PX) will be highly valued.
In this role, you will work closely with the team on floorplanning at cutting-edge technology nodes, developing and optimizing synthesis and place & route flows, integrating multiple custom blocks, and running comprehensive power analysis on the resulting P&R netlists.
Requirements:
* Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field
* Proficiency with EDA tools from Synopsys, Cadence, or Mentor
* Strong scripting skills (Tcl preferred)
* 7+ years of relevant industry experience
* Minimum of 2 successful tape-outs
* Solid understanding of physical design verification and sign-off methodologies (timing closure, DRC, LVS)
* Familiarity with DFT methods and Tessent flow (a strong plus)