Physical ASIC Design Implementation Engineer
Position Type: 12-Month Contract (with potential for extension)
Location: Leuven, Belgium (Hybrid: 3 days on-site)
A pioneer in cutting-edge semiconductor research and digital technology is looking for a skilled Physical ASIC Design Implementation Engineer for a 12-month contract. Based in Leuven, Belgium, this role operates on a hybrid model, allowing you to combine remote work with vital on-site collaboration at a world-class facility.
The company delivers advanced chip design solutions across a vast spectrum of technologies, ranging from mature 180nm nodes down to leading-edge N2 processes. This role offers the opportunity to drive full backend Place & Route (P&R) projects from netlist-in to GDSII-out.
The Role
As a technical lead and primary contact for customers, you will guide physical implementation across the entire chip design cycle to achieve sign-off closure for tape-out.
Key responsibilities:
* Acting as the technical voice to the customer to discuss design specifications and future projects.
* Utilizing a comprehensive understanding of the complete Cadence Innovus Place & Route flow.
* Taking the lead on chip partitioning and splitting top-level SDC files into timing budget requirements and constraints for sub-blocks.
* Working closely with the Physical Design implementation team to drive successful tape-out.
Profile & Experience
* Flow & Node Setup: Proven experience setting up the implementation flow for specific library sets and foundry nodes.
* Low Power & Constraints: Hands-on experience setting up low-power designs (UPF) and debugging SDC files.
* Design Execution: Strong knowledge of floorplanning and power grid design for both top-level chips and individual blocks, including Placement, CTS, and Routing.
* Timing & Closure: Deep expertise in solving setup and hold violations.
* Sign-off Tools: Proficient in sign-off extraction (SPEF/Quantus), timing (Tempus), and power analysis (Voltus).
* Verification: Comprehensive understanding of physical verification (DRC, ERC, LVS, ANT) and logic equivalence checking.
Interested? Apply directly through LinkedIn, or send your CV to george@eu-recruit.com
By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)