We are looking for an experienced Physical ASIC Design Implementation Engineer to join an exciting semiconductor project, working across the complete backend implementation flow from netlist to GDSII.
You will be responsible for delivering full Place & Route (P&R) implementation across both top-level chips and block-level designs, working on advanced technologies ranging from N2 through to 180nm. This role requires strong expertise across the complete Cadence Innovus implementation flow and the ability to drive designs successfully through to tape-out.
Location: 3 days per week onsite in Leuven.
Contract length: 1 year with extensions
Employment: Contract/freelance
Responsibilities:
* Own and support full backend physical implementation activities from netlist through to GDSII
* Work closely with customers to understand requirements and provide technical guidance throughout projects
* Lead partitioning activities and translate top-level SDC constraints into timing budgets and requirements for sub-blocks
* Collaborate with Physical Design teams throughout the chip development lifecycle to achieve successful signoff and tape-out
* Act as a key technical point of contact, discussing specifications, challenges, and solutions directly with customers
* Drive implementation, optimisation, and closure across complex ASIC designs
Required Experience:
* Strong experience with the complete Cadence Innovus Place & Route flow
* Experience setting up implementation flows for specific foundry nodes and technology libraries
* Knowledge of low-power design methodologies (UPF) and SDC constraint debugging
* Hands-on experience with:
* Floorplanning and power grid design (top-level and block-level)
* Placement, Clock Tree Synthesis (CTS), and Routing
* Setup and hold timing closure
* Signoff extraction (SPEF / Quantus)
* Static Timing Analysis using Tempus
* Power analysis using Voltus
* Physical verification including DRC, ERC, LVS, ANT checks
* Logic Equivalence Checking (LEC)
This is a fantastic opportunity to work on complex semiconductor designs, collaborating with expert engineering teams and contributing to next-generation ASIC technologies.
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