Design Verification Engineer
Location : Pan India
Experience : 4 to 12 Years
Key Skills
* SystemVerilog (SV), UVM, VHDL
* Synopsys VCM, Verdi, Formality
* Mentor Graphics Questa or similar tools
* Technologies: PCIe, Ethernet, RISC-V processors
Roles And Responsibilities
* Demonstrated knowledge and experience in design verification processes and methodologies, preferably for complex SoCs/designs.
* Develop and execute verification plans using SystemVerilog and UVM to validate complex ASIC/FPGA designs.
* Design and implement testbenches and verification environments to ensure functional accuracy and performance.
* Debug and troubleshoot complex issues, providing detailed analysis and solutions.
* Document verification processes, methodologies, and results to ensure clarity and reproducibility.
* Hands-on experience with formal verification methodologies.
* Experience in functional verification methodologies and simulations.
* Working experience with Ethernet and PCIe protocols.
* Experience in verifying low power designs.
* Ability to interact and coordinate effectively with cross-functional teams.
* Strong communication skills to facilitate collaboration and project success.
Qualifications
* Highest Qualification: B.Tech B.E. Electrical M.Tech Others
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