*Perform RTL synthesis and optimize for timing, area, and power.
*Execute DFT (Design-for-Test) insertion using industry-standard tools.
*Conduct Logical Equivalence Checking (LEC) to validate design integrity.
*Generate and validate ATPG (Automatic Test Pattern Generation) patterns.
*Improve test coverage through advanced methodologies.
*Run pre-layout and post-layout test pattern simulations to ensure robustness.
*Collaborate closely with physical design teams for seamless RTL-to-GDS integration.
*Utilize Cadence or Synopsys EDA tools for synthesis, DFT insertion, and ATPG.
*Apply Tessent (Siemens) tools for DFT insertion and ATPG in specific projects.
*Troubleshoot and resolve design issues across the front-end flow.
*Document design processes and contribute to continuous improvement initiatives.
*Engage with internal and external stakeholders to deliver high-quality design services.
Profile / Requirements :
*5+ years of experience in ASIC front-end design, including RTL-to-GDS flow.
*Proven expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement.
*Hands-on experience with Cadence (preferred) (Genus, Modus, Conformal, Xcelium, etc.) and-or Synopsys toolsets (DC, FC, TestMAX, SpyGlass, etc.).
*Familiarity with Tessent tools for DFT and ATPG.
*Solid understanding of digital design principles, timing closure, and test strategies.
*Proficiency in Verilog or SystemVerilog and scripting languages (Tcl, Python, etc.).
*Strong problem-solving skills and ability to work in cross-functional teams.
*Excellent communication skills and attention to detail.
*A masters degree in Electrical Engineering, Computer Engineering, or related field