For our client, we are seeking a 3DIC Physical Design Engineer to work on cutting‑edge 3D integration technologies, driving innovation in next‑generation semiconductor systems. We’re hiring on behalf of a leading global research center pioneering the future of chip integration. Join an international R&D team working at the edge of semiconductor innovation: 2.5D/3DIC design, Chiplet integration, and advanced physical implementation flows. Your Role As a 3DIC Physical Design Engineer, you’ll develop and implement physical design strategies for complex multi-die systems. You’ll help shape the next generation of high-performance, low‑power chip architectures. Design high‑speed clock buses across dies to meet strict PPA (Power, Performance, Area) targets Contribute to floorplanning, interconnect, power delivery, and thermal design in 2.5D/3DIC systems Define and apply signoff methodologies for multi-die integration Support STCO/DTCO initiatives to co‑optimize architecture and technology Collaborate with experts across architecture, design, packaging, and fabrication What We’re Looking For Technical Expertise Proven experience in back‑end physical implementation, with large‑scale chip design and verification (RTL2GDS) Solid understanding of physical design flows, EDA tools (e.G., Cadence, Synopsys), and timing closure techniques Hands‑on experience with high‑speed bus planning, 3DIC or Chiplet designs Familiarity with advanced semiconductor processes (e.G., FinFET, 7nm/5nm), including design rules and process constraints Knowledge of reliability, power integrity, and thermal management in multi‑die systems Experience translating system/product requirements into chip architecture and floorplan strategies Qualifications Master’s degree or PhD in Electronics, Computer Engineering, Physics, Materials Science, or related field 5–10 years of relevant industry experience Be part of a team redefining how the most advanced chips are physically built. Contact Antal International Paris London #J-18808-Ljbffr