We are seeking an experienced Senior Analog Layout Engineer to design and integrate complex analog and GPIO circuits for advanced process technologies (e.g., TSMC 16nm and below) as well as deep sub-micron nodes. As part of our innovative research team, you will take full ownership of schematic-to-layout implementation, top-level integration, and layout sign-off-ensuring best-in-class performance, reliability, and manufacturability. This role requires close collaboration with analog design, PDK, and EDA tool teams to deliver robust, high-quality layouts that meet stringent foundry and reliability standards.
Key responsibilities
* Execute end-to-end schematic-to-layout design for analog and GPIO circuits.
* Perform floor planning, IO pad-ring design, ESD implementation, and top-level integration.
* Conduct full physical verification (DRC, LVS, Antenna, Density, ERC, EMIR & PEX) and ensure compliance with foundry and reliability standards.
* Optimize layout for matching, symmetry, shielding, and parasitic control to achieve superior performance and yield.
* Collaborate with circuit design teams for layout correlation, simulation feedback, and sign-off support.
* Document layout methodologies, checklists, and best practices; contribute to layout automation and process improvement.
* Participate in cross-functional reviews to maintain high-quality standards and continuous improvement.
Job profile
* Bachelor's or Master's degree in Microelectronics, IC Design or equivalent.
* 8+ years of hands-on experience in analog/mixed-signal IC layout for advanced FinFET and CMOS technologies.
* Proven expertise with Tanner, Cadence Virtuoso, and Calibre tools for layout and verification environments.
* Strong understanding of PCELLS/pycells, PDK Components, floor planning, power grid, IO ring, and ESD integration.
* In-depth knowledge of Layout-Dependent Effects (LDE), EM/IR analysis, and reliability considerations.
* Solid grasp of analog layout fundamentals—including matching, shielding, low-noise design, and electromigration constraints.
* Ability to work both independently and as a team player, managing multiple deliverables and coordinating effectively with project leads.
* Excellent communication, problem-solving, and documentation skills.
* Python/Tcl scripting knowledge is a plus.
* Fluency in English or Dutch (written and spoken).
* Willingness to relocate within commuting distance (our location is Aalter, Belgium).
Offer
You will join an SME with an extensive international customer base, healthy finances and strong growth potential. We offer a competitive and attractive salary package with various fringe benefits; we offer the opportunity for continuous learning, both through external and internal training. You will become part of our dynamic engineering team and work with top semiconductor companies worldwide.
We offer the flexibility of a start-up, the stability of an established, profitable and robust company, with facilities and benefits that match or exceed any other opportunity in our industry.
Because we value this, we operate out of a self-designed BEN (nearly energy neutral, an official label) building with spacious workstations, state-of-the-art lab and pleasant rest and meeting spaces. We also facilitate a personalized mix of office and home work.
Contract
Permanent contract – indefinite duration
How to
Eager to contribute to the next wave of micro and nano semiconductor innovations? We want to hear from you Send us your CV along with your interests to
At Sofics, we're not just growing; we're thriving, thanks to talents like you. Join us, and let's create lasting value together.