Join to apply for the Principal Virtual Platform Architect role at imec.
**What you will do:**
The compute system architecture (CSA) is a center of excellence at imec for HW-SW co-design for future compute systems.
As a Principal [Virtual] Platform Architect in CSA at imec, you will be responsible for gathering and processing requirements from customers (internal/external) on system architecture, and for translating them to build system-level virtual platforms that meet those requirements. This includes pathfinding/de-risking future system architectures, especially for sectors such as HPC/AI/Automotive.
This role combines research, software engineering, and hardware modeling. You will work with colleagues and stakeholders with backgrounds in these areas, using in-house or industry-standard virtual platform modeling tools (e.g., Gem5, QEMU, ARM Fast Models, or tools from Synopsys, Cadence). Your work will ensure the virtual platform accurately reflects the hardware design and supports software/workload developers.
You will also contribute to developing a scalable modeling and simulation strategy to enhance operational efficiency.
What We Do For You
Join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. We foster an inclusive, multicultural, and informal environment, supporting your growth through imec.academy. Your contributions are valued with a competitive salary and benefits.
Who You Are
* Master’s or Doctoral degree in Computer Science or Electrical/Computer Engineering
* 8+ years (6+ post PhD) of relevant industrial experience, including high-level requirements intake/definition; strong applicants with slightly less experience are encouraged to apply
* Deep knowledge of computer architecture and microarchitecture, including SoC architectures, CPUs, GPUs, memory subsystems, and interconnects
* Experience with system-level virtual platform modeling (e.g., Gem5, QEMU, ARM Fast Models) and delivering insights on performance, power, and feasibility
* Strong RTL design experience (Verilog, SystemVerilog, VHDL)
* Experience with SystemC/TLM for hardware/software co-design modeling
* Experience integrating transaction-level and RTL simulations for performance analysis or verification
* Expertise in debugging and analysis at the system level (power, performance, etc.)
* Good software/hardware engineering practices (version control, CI, testing)
* Hands-on approach and mentorship skills to foster a culture of creativity and collaboration
* (Optional) Experience with RISC-V ecosystem
Additional Details
* Seniority level: Mid-Senior level
* Employment type: Full-time
* Job function: Engineering and IT
* Industry: Research Services
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