Overview
DFT Engineer
Location: Pan India
Responsibilities
* Develop and implement Design for Test (DFT) strategies for ASIC designs.
* Perform scan insertion, Automatic Test Pattern Generation (ATPG), and Built-In Self-Test (BIST) implementation.
* Work with JTAG and boundary scan techniques.
* Collaborate with design and verification teams to integrate DFT features into the design.
* Utilize CAD tools such as Cadence and Synopsys for DFT implementation and verification.
* Debug and resolve DFT-related issues during the design and testing phases.
* Ensure testability and manufacturability of the design, meeting industry standards and specifications.
* Document DFT methodologies and provide clear reports to the design team.
Qualifications
* Experiences: 4 to 12 years (Fresher to 10+ years as referenced in original content).
* Key skills: Design for Test (DFT), Scan Insertion, ATPG, JTAG, BIST, Verilog, VHDL, Cadence Modus/Xcelium, Synopsys DFTMAX/TetraMax, Mentor Graphics Tessent.
* Highest Qualification: B.Tech / B.E. / Electrical / M.Tech / Others.
* Standard Notice Period: 1 Month / 2 Months / 3 Months.
* Currently Serving Notice: Immediate / 15 Days / 30 Days / 45 Days / 60 Days / 75 Days / 90 Days.
Additional Notes
This description focuses on role responsibilities and required qualifications. It omits non-job content such as marketing, navigation menus, and contact/promotional details. All content is kept to the essential information necessary to define the role for applicants.
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