A semiconductor development company in Belgium is seeking a Senior ASIC Back-End Design Engineer for a 6-month contract. The candidate will drive RTL synthesis activities, implement DFT architectures, and ensure design consistency through LEC. With a minimum of 5 years in ASIC digital implementation, the role demands expert knowledge in the RTL-to-GDSII flow, Proficiency in Verilog, and experience with industry-standard EDA tools. Join a dynamic team to optimize complex digital IC designs in an advanced technical environment.
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