Ph3Digital SoC Design Engineer (temporary assignment) /h3 pWe need you as a Digital IC Design Engineer to be part of our multidisciplinary team to: Define concepts and architectures for next generation ICs for IoT, edge AI accelerator ICs and Health applications ICs. Take responsibility for the design of high-performance, ultra-low-power digital signal processing modules. /p h3The assignment /h3 ul liComing up with digital architectures. /li liRTL development for ASIC and FPGA. /li liMaking trade-offs for minimal power consumption at best performance and low cost, while considering scalability, maintainability and re-usability. /li liCollaborate with digital back-end team for synthesis and physical implementation. /li liVerification. /li liValidate and characterize your own designs experimentally in a lab environment. /li liCollaborate in an inter-disciplinary team. /li liUnderstand (internal or external) customer needs, challenges and requirements and translate that into solutions that you can incorporate into your designs. /li liContribute to high-quality reports and documentation. /li /ul h3Required knowledge and skills /h3 ul liMSc or PhD in electronics engineering with 5+ years of relevant experience. /li liStrong experience with digital circuit design in (System) Verilog is required. /li liFollowing application experience is a preferred: Affiliation on hardware efficient AI accelerator, event driven computing, compute modalities like multi-core -processor systems, in memory computing, large data computing. /li liHardware modelling. Architecting and designing CPU and peripheral (sub-)systems. /li liExperience with digital verification is preferred: verification plan definition and tracking, verification methodologies, code-functional coverage, constrained random verification. /li liUnderstanding of the remaining steps of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and-or PR. /li liExperience with scripting languages like TCL, Matlab and Python is required. /li liExperience with revisioning systems, like git is required. /li liKnowledge of FPGA-development is a plus. /li liKnowledge of low-power designs is a plus. /li liExperience with Cadence IC design tools is a plus. /li liExperience with C and systemC is a plus. Structural way of working and ability to develop and manage activity planning is highly preferred. /li liPrevious experience working closely with (internal or external) stakeholders is a plus. /li liAble to take initiative and responsibility for team’s success. /li liThinking pro-actively, working independently and having a creative problem-solving attitude are attributes that define yourself. /li liHave broad interest across disciplines and like to embrace new challenges. /li liExcellent communication skills in English (written and spoken). /li /ul h3What we offer /h3 pWe offer you an exciting temporary assignment in which you will be part of a community that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow. /p ul liDuration of the assignment, 6 months, with extension if applicable /li liDesired start date: 16/03/2026 /li liWork regime: full time /li /ul h3Location /h3 pWe provide the flexibility to work both from our office premises and remotely from home. This to maintain a healthy work-life balance while being an integral part of our team. But an onsite presence of 3 days a week is required. It\'s not possible to work 100% remote. /p pb*Agencies can only present candidates if explicitly invited by flexforce to our agency portal. Only candidates presented via the agency portal are linked to an agency in our system. Please don\'t upload candidates via the regular "apply" button as they will not be allocated to your agency in our system and we will not be able to follow up. /b /p /p #J-18808-Ljbffr