We are looking for an experienced Physical Implementation Engineer to work on full backend Place & Route (P&R) projects covering the complete flow from netlist-in to GDSII-out.
The role involves working on both top-level chip integration and block-level implementation, across technologies ranging from N2 to 180nm. The position requires a deep understanding of the Cadence Innovus Place & Route flow and collaboration with design and implementation teams to achieve successful tape-out signoff.
Responsibilities
* Execute full Physical Implementation (P&R) from netlist-in to GDSII-out.
* Work on both top-level chip designs and block-level implementations.
* Maintain direct contact with customers to support and discuss future projects.
* Provide technical guidance and interface with customers to clarify design specifications.
* Lead partitioning activities and split the top-level SDC into timing budget requirements for sub-blocks.
* Collaborate closely with the Physical Design implementation team throughout the chip design cycle.
* Drive timing, power, and physical sign-off closure for successful tape-out.
Required Skills & Experience
* Strong experience with the Cadence Innovus Place & Route flow.
* Experience setting up implementation flows for specific libraries and foundry nodes.
* Experience with low-power design setup (UPF) and SDC debugging.
* Solid knowledge of floorplanning and power grid design for both top-level and block-level implementations.
Physical Design Expertise
* Placement, Clock Tree Synthesis (CTS), and Routing
* Resolution of setup and hold timing violations
* Sign-off extraction (SPEF / Quantus)
* Static timing analysis (Tempus)
* Power analysis (Voltus)
* Physical verification (DRC, ERC, LVS, ANT)
* Logic equivalence checking