Advanced characterization and understanding of 2D FETs
Pushing the boundaries of 2D semiconductor scaling with optimized interfaces and reliable gate stacks.
Performanceand scalability of MoS₂ FETs are strongly constrained by contact resistance, Fermi‑level pinning, and gate‑stack limitations such as interfacetraps, dielectric deposition challenges, and high operating voltages. Improving both the contact interface and the gate dielectric stack is essential for enabling low‑power, high‑performance 2D electronics. [arxiv.org] ,[science.org]
Objectives
* Engineer low‑damage, low‑resistance contacts using metals with favourable interaction to MoS₂ (e.g., Ni, Ti, Y) by studying interface chemistry, band alignment, and deposition‑induced defects.
* Develop high‑quality gate stacks using ultra‑thin high‑κ dielectrics (Al₂O₃/HfO₂/ZrO₂). Correlate structural, electrical, and thermal reliability up to compatible BEOL temperatures.
* Provide support on electrical characterization and modelling of ferroelectric memories (FeFET and FeRAM).
Requirements
* Background in Electrical Engineering, semiconductor physics, quantum physics, semiconductor device reliability.
* Experience with electrical characterization of electronic devices.
* Experience in the semiconductor industry.
* Internship up to 1 year, self‑supported PhD student.
Type of internship: PhD internship
Duration: up to 1 year
Required educational background: Electrotechnics/Electrical Engineering
University promotor: Clement Merckling (KU Leuven)
Supervising scientist(s): For further information or for application, please contact Bogdan Govoreanu (Bogdan.Govoreanu@imec.be) and Xiangyu Wu (Xiangyu.Wu@imec.be) and Nicolo Ronchi (Nicolo.Ronchi@imec.be)
The reference code for this position is 2026-INT-040. Mention this reference code in your application.
Only for self‑supporting students.
Applications should include the following information:
* Resume
* Motivation
* Current study
Incomplete applications will not be considered.
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