Your AssignmentAs a Digital SoC Expert Designer and Technical Leader, you will:Collaborate with system architects, digital back-end engineers, embedded software developers, and validation teams.Lead RTL development for ASICs and FPGAs, supervising verification planning and execution (including mixed-signal projects where relevant).Define and propose innovative ways of working to maximize design process efficiency.Contribute to high-quality technical reports and documentation.Required Knowledge & SkillsMSc or PhD in Electronics Engineering with 10+ years of relevant ASIC design experience.Strong understanding of digital ASIC design flow: logic synthesis, timing analysis, power estimation/simulation, logic equivalence, STA. DFT and/or P&R experience preferred.Structured approach to work and ability to develop and manage activity planning.Experience collaborating with internal and external stakeholders.Proficient in digital circuit design using (System) Verilog.Experience with SoC top-level design and sub-systems, including low-power techniques.Preferred: experience with digital verification (plan definition, methodologies, coverage, constrained random verification, plan execution & tracking).Plus: knowledge of high-level synthesis methodologies.Experience with Cadence IC design tools preferred.Knowledge of FPGA development flow is a plus.Skilled in scripting languages (TCL, MATLAB, Python).Experience with revisioning systems (e.G., Git).Initiative-taking, independent, pro-active, and creative problem-solving mindset.Broad interest across disciplines and ability to embrace new challenges.Excellent English communication skills (written and spoken).