Physical ASIC Design Implementation Engineer — Physical Design / Place & Route / Backend Implementation
We are partnered with a world-renowned research and innovation hub in semiconductor and nanotechnology. The team is looking to hire a Physical ASIC Design Implementation Engineer to lead full backend P&R projects from netlist-in to GDSII-out, across technology nodes ranging from N2 to 180nm.
This is an initial 12-month contract opportunity based in Leuven, Belgium, working on a hybrid basis.
Key responsibilities for this Physical ASIC Design Implementation Engineer position:
* Own full backend implementation projects from netlist-in to GDSII-out using Cadence Innovus.
* Lead top-level SDC partitioning and translate timing budgets into sub-block constraints.
* Drive signoff closure for tape-out in close collaboration with the Physical Design implementation team.
* Act as the technical point of contact for customers, discussing specifications and managing future projects.
Key requirements:
* Expertise in the full Cadence Innovus Place & Route flow.
* Experience setting up flows for specific library sets and foundry nodes.
* Hands-on experience with low power design (UPF) and SDC debug.
* Strong knowledge of floorplanning, power grid design, CTS, and routing.
* Experience resolving setup and hold violations.
* Proficiency in signoff tools: SPEF/Quantus (extraction), Tempus (timing), Voltus (power analysis).
* Experience with physical verification — DRC, ERC, LVS, ANT — and logic equivalence checking.
Keywords: Physical ASIC Design Engineer / Backend Implementation / Place & Route / P&R / Cadence Innovus / GDSII / SDC / UPF / Low Power Design / Floorplanning / CTS / Timing Closure / Tempus / Voltus / Quantus / SPEF / DRC / LVS / Tape-out / Semiconductor / Leuven / Belgium / Hybrid / Contract
If you are interested in this Physical ASIC Design Implementation Engineer position, please send a copy of your CV to ts@eu-recruit.com
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