Client Background & Position Overview
Our client is a globally recognized leader in ICT and semiconductor research, with a strong commitment to pushing the boundaries of technology. Their European Research Institute (ERI), located in Leuven, Belgium, serves as a hub for advanced semiconductor R&D, focusing on disruptive technologies and next-generation process nodes.
As part of the DTCO (Design-Technology Co-Optimization) team, the selected engineer will play a key role in optimizing device architectures, process technologies, and design methodologies, to drive innovations in semiconductor PPA, reliability, and manufacturability.
Responsibilities
* Lead DTCO (Design-Technology Co-Optimization) activities for advanced process nodes by collaborating with fab, design, and product teams.
* Define technology architecture and optimization directions to improve process capabilities and enhance PPA (Power, Performance, Area).
* Develop and optimize device types, standard cells, and SRAM architectures aligned with PPA targets.
* Define Design Rule Manual (DRM) constraints and support process guideline development.
* Identify risks related to OPC (Optical Proximity Correction), DFM (Design for Manufacturability), and DFR (Design for Reliability) and propose mitigation strategies.
* Provide feedback from module-level physical design to influence SoC-level optimizations, including PDN (Power Delivery Network) design, metal stack choices, and design flows.
* Create benchmarking methodologies, analyze process/design trade-offs, and provide guidance for competitive technology development.
* Conduct research on industry DTCO trends, competitive analysis, and contribute to the roadmap for future technology platforms.
Requirements
* Master’s or PhD in Microelectronics, Semiconductor Engineering, Electronics, Physics, Materials Science, or related fields.
* 5–10 years of hands-on experience in DTCO, process integration, circuit design, or semiconductor technology development.
* Solid knowledge of semiconductor process flows, device physics, ground rules, and design methodologies.
* Proficiency with PDKs, circuit design and simulation, physical layout, RC extraction, and Place & Route tools.
* Deep understanding of standard cell and SRAM design, process rule development (DRM), and technology scaling impacts.
* Experience with OPC, DFM, and DFR methodologies.
* Strong skills in PPA benchmarking and data-driven optimization.
* Demonstrated ability to work in cross-functional and international teams, with an innovation-driven mindset.
If you are excited about the opportunity to shape the future of semiconductor technology through DTCO, we encourage you to apply. Join a pioneering research environment where your expertise will directly contribute to next-generation innovation, impacting both technology development and product excellence.