As a Physical ASIC Design Implementation Engineer, you are mainly responsible for the physical design of chips: translating a logical chip design (netlist) into a concrete layout that can be manufactured in a foundry.
In this role, you are responsible for:
1. From netlist to layout
After the work of the digital designers (RTL/design), the engineer receives a netlist (logical description of the chip).
This is transformed into a physical design using tools such as Cadence Innovus:
* Placement of standard cells
* Clock Tree Synthesis (CTS)
* Routing: connecting everything using metal layers
2. Floorplanning & power design
* Defining the chip layout (placement of different blocks)
* Designing the power grid (distributing power across the chip)
* Taking into account size, performance, and power consumption
3. Timing optimization
The chip must operate both quickly and correctly:
* Verifying signal timing (setup & hold checks)
* Resolving timing violations
* Working with constraints (SDC files)
4. Low power & efficiency
* Implementing techniques to reduce power consumption (e.g. using UPF)
* Balancing performance, power, and area (PPA)
5. Sign-off & verification
Before the chip goes into production:
* Timing analysis
* Power analysis
* Physical verification checks:
* DRC (design rule checks)
* LVS (layout vs schematic)
* Parasitic extraction (SPEF)
Goal: ensuring the chip can be manufactured flawlessly.