Physical ASIC Design Implementation Engineer — Physical Design / Place & Route / Backend Implementation
The team is looking to hire a Physical ASIC Design Implementation Engineer to lead full backend P&R projects from netlist-in to GDSII-out, across technology nodes ranging from N2 to 180nm.
This is an initial 12-month contract opportunity based in Leuven, Belgium, working on a hybrid basis.
Key responsibilities for this Physical ASIC Design Implementation Engineer position:
Own full backend implementation projects from netlist-in to GDSII-out using Cadence Innovus.
Drive signoff closure for tape-out in close collaboration with the Physical Design implementation team.
Experience setting up flows for specific library sets and foundry nodes.
Hands-on experience with low power design (UPF) and SDC debug.
Strong knowledge of floorplanning, power grid design, CTS, and routing.
SPEF/Quantus (extraction), Tempus (timing), Voltus (power analysis).
Physical ASIC Design Engineer / Backend Implementation / Place & Route / P&R / Cadence Innovus / GDSII / SDC / UPF / Low Power Design / Floorplanning / CTS / Timing Closure / Tempus / Voltus / Quantus / SPEF / DRC / LVS / Tape-out / Semiconductor / Leuven / Belgium / Hybrid / Contract
If you are interested in this Physical ASIC Design Implementation Engineer position, please send a copy of your CV to ts@eu-recruit.By applying to this role you understand that we may collect your personal data and store and process it on our systems.