Physical ASIC Design Implementation Engineer
A fantastic opportunity for a skilled Physical Design Implementation Engineer to join a globally renowned Research and Development Centre, working on next generation microchips.
This is initially a 12 Month Contract with option to extend.
Responsibilities
* Direct contact with our customers for future projects.
* Full understanding of the complete Cadence Innovus Place & Route flow.
* Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
* Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
* Technical voice to the customer to discuss his specifications
Required knowledge and skills
* Experience in setting-up the flow for the specific library set and foundry node used
* Experience in setting-up low power design (UPF) and debug sdc file
* Knowledge in Floorplanning & power grid design for toplevel aswell as blocks
- Place, CTS & Routing
- Solve setup & hold violations
- Sign-off extraction (SPEF/QUANTUS), timing (TEMPUS), Power analysis (VOLTUS)
- Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check
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