Physical ASIC Design Implementation Engineer
We are looking for a Physical ASIC Design Implementation Engineer to support full back‐end (Place & Route) projects, covering the complete flow from netlist-in to GDSII-out. You will work on both top-level chips and block-level designs, across technology nodes ranging from N2 to 180nm, with a strong focus on the Cadence Innovus Place & Route flow .
This is a hands-on technical role that combines deep physical design expertise with direct customer interaction.
Key Responsibilities
* Execute full physical implementation flows (P&R) from netlist to GDSII for top-level and block-level designs
* Own and apply an in-depth understanding of the complete Cadence Innovus Place & Route flow
* Take the lead in top-level partitioning and split the top-level SDC into timing budgets and constraints for sub-blocks
* Work closely with the Physical Design implementation team throughout the entire chip design cycle
* Drive sign-off and tape-out readiness
* Act as the technical interface to customers, discussing specifications and future project requirements
* Maintain direct contact with customers to support ongoing and upcoming projects
Required Knowledge and Skills
* Proven experience in setting up physical design flows for specific library sets and foundry nodes
* Experience with low-power design methodologies (UPF) and debugging SDC files
* Strong knowledge of:
* Floorplanning and power grid design (top-level and block-level)
* Placement, Clock Tree Synthesis (CTS), and routing
* Setup and hold timing closure
* Sign-off expertise including:
* Parasitic extraction ( SPEF / Quantus )
* Timing analysis ( Tempus )
* Power analysis ( Voltus )
* Physical verification:
* DRC, ERC, LVS, antenna checks
* Logic equivalence checking (LEC)
What We Offer
* An exciting assignment within an advanced technology environment
* The opportunity to be part of a community that pushes the limits of what is possible
* A role contributing directly to technologies that will shape the society of tomorrow
Interested?
anne@bimona.be