Physical ASIC Design Implementation EngineerWe are looking for a Physical ASIC Design Implementation Engineer to support full back‑end (Place & Route) projects, covering the complete flow from netlist-in to GDSII-out. You will work on both top-level chips and block-level designs, across technology nodes ranging from N2 to 180nm, with a strong focus on the Cadence Innovus Place & Route flow.This is a hands-on technical role that combines deep physical design expertise with direct customer interaction.Key ResponsibilitiesExecute full physical implementation flows (P&R) from netlist to GDSII for top-level and block-level designsOwn and apply an in-depth understanding of the complete Cadence Innovus Place & Route flowTake the lead in top-level partitioning and split the top-level SDC into timing budgets and constraints for sub-blocksWork closely with the Physical Design implementation team throughout the entire chip design cycleDrive sign-off and tape-out readinessAct as the technical interface to customers, discussing specifications and future project requirementsMaintain direct contact with customers to support ongoing and upcoming projectsRequired Knowledge and SkillsProven experience in setting up physical design flows for specific library sets and foundry nodesExperience with low-power design methodologies (UPF) and debugging SDC filesStrong knowledge of:Floorplanning and power grid design (top-level and block-level)Placement, Clock Tree Synthesis (CTS), and routingSetup and hold timing closureSign-off expertise including:Parasitic extraction (SPEF / Quantus)Timing analysis (Tempus)Power analysis (Voltus)Physical verification:DRC, ERC, LVS, antenna checksLogic equivalence checking (LEC)What We OfferAn exciting assignment within an advanced technology environmentThe opportunity to be part of a community that pushes the limits of what is possibleA role contributing directly to technologies that will shape the society of tomorrowInterested?anne@bimona.be