We have an exciting opportunity for a Senior Digital Design Verification Engineer to join a new product development team in Leuven, Belgium. Location: Leuven, Belgium – minimum 3 days in office Type: Freelancer | 100% FTE (40 hours/week) Duration: 6 months Start Date: Immediate start Hourly Rate: €70–73/per hour Role Overview We are building a new product development team in Leuven and are seeking a skilled engineer in digital IC hardware verification. This role involves verifying blocks, subsystems, or top-level functions, developing testbenches, and collaborating with cross-functional teams to ensure successful product delivery. Key Responsibilities Take ownership of verification for assigned blocks/subsystems Develop and implement testcases using SystemVerilog, UVM, Python, and assertions Maximize verification coverage and maintain regression suites Participate in design reviews, peer reviews, and root-cause analysis Collaborate with cross-functional teams (Analog, Firmware, Layout) Candidate Profile / Key Skills Education: Master’s in Electronic/Electrical Engineering Experience: 5–10 years in digital IC design/verification Strong knowledge in UVM, SystemVerilog, and Assertion-Based Verification Proven experience delivering high-volume silicon Familiarity with low-power design techniques; experience in audio or AI accelerators is a plus Hands-on experience with Cadence EDA tools, Synopsys Spyglass, VHDL/Verilog/SystemVerilog, Python Strong analytical and debugging skills Excellent team player with strong communication skills; fluent in English If this sounds like a fit and you’re interested, I would love to arrange a quick conversation to share more details. Please feel free to share your CV with me Looking forward to your thoughts. Best regards, Tee