Ph3Position /h3 pDesign Verification Engineer /p h3Location /h3 pPan India /p h3Experience Required /h3 p4 to 12 Years /p h3Key Skills /h3 ul liSystemVerilog (SV), UVM, VHDL /li liSynopsys VCM, Verdi, Formality /li liMentor Graphics Questa or similar tools /li liTechnologies: PCIe, Ethernet, RISC-V processors /li /ul h3Responsibilities /h3 ul liDemonstrated knowledge and experience in design verification processes and methodologies, preferably for complex SoCs/designs. /li liDevelop and execute verification plans using SystemVerilog and UVM to validate complex ASIC/FPGA designs. /li liDesign and implement testbenches and verification environments to ensure functional accuracy and performance. /li liDebug and troubleshoot complex issues, providing detailed analysis and solutions. /li liDocument verification processes, methodologies, and results to ensure clarity and reproducibility. /li liHands-on experience with formal verification methodologies. /li liExperience in functional verification methodologies and simulations. /li liWorking experience with Ethernet and PCIe protocols. /li liExperience in verifying low power designs. /li liAbility to interact and coordinate effectively with cross-functional teams. /li liStrong communication skills to facilitate collaboration and project success. /li /ul h3Contact /h3 /p #J-18808-Ljbffr