ASIC DESIGN ENGINEER - ANTWERP (BELGIUM) - PERMANENT POSITION
We're a fast-moving startup on a mission to redefine how the world connects, who are currently recruiting for an ASIC Design Engineer who will help to build the future of telecom from the ground up.
In this role, you'll have real ownership over the design and development of custom ASICs that sit at the heart of next-gen communication systems.
Think high-speed data paths, ultra-efficient processing, and hardware that pushes the limits of what's possible in 5G/6G networks, edge computing, and beyond.
You'll be working closely with a tight-knit, cross-functional team of architects, RF designers, software folks, and systems engineers to bring ideas from whiteboard to silicon.
Key Responsibilities:
* Architect, design, and implement ASIC solutions for telecom applications such as high-speed networking, signal processing, and protocol handling.
* Develop RTL code using Verilog/SystemVerilog or VHDL for digital logic design.
* Perform block-level and top-level simulations and functional verification.
* Collaborate with system architects, RF engineers, firmware, and software teams to ensure seamless hardware-software integration.
* Optimize designs for power, performance, and area (PPA) to meet stringent telecom requirements.
* Work closely with physical design and DFT teams to ensure a smooth handoff and integration.
* Support post-silicon validation and bring-up of ASICs in lab environments.
* Contribute to continuous improvement of design flows, methodologies, and best practices.
Required Qualifications:
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
* 3+ years of experience in ASIC design, preferably in the telecommunications or networking domain.
* Strong proficiency in RTL design using Verilog/SystemVerilog or VHDL.
* Solid understanding of digital signal processing, data path design, and high-speed interfaces (e.g., SERDES, Ethernet, PCIe).
* Familiarity with communication protocols such as LTE, 5G NR, IP, or SONET/SDH is a plus.
* Experience with EDA tools for synthesis, simulation, static timing analysis (STA), and linting.
* Good grasp of design verification methodologies (UVM, SystemVerilog assertions, coverage analysis).
The Offer:
* A permanent, full-time employment contract
* A salary & benefits package commensurate with experience
Please send over your CV to tom.walker@vividresourcing.com or call me on +32 (0) 3 318 00 74. As always, we are open to recommendations, so please feel free to pass this on to other suitable candidates.